In order to establish a reliable connection between substrate and chip, a bumping process has been developed that enables the SMD assembly technique to be expanded by using flip chips. An essential prerequisite for the bumping process with all the related assembly demands of placing tin bumps on the pads with optimum soldering properties has still to be found. Solutions are being developed that make bumping on the chip and assembly of the chip on the substrate possible in accordance with today's quality requirements. This includes the affixing of the Ni and Au layer to the pad for the actual bumping process, the cleaning of the wafer after reflow soldering and the preparation of the later assembly. All chips are not the same and therefore regulations and specifications have to be worked out to achieve this Ni/Au bumping process successfully on a range of wafer types. We speak of " UBMs" (under bump metallization).
| Pitch intervals and bumping height
Chips with a low surface and correspondingly few pads can be transformed into flip chips using the cited prerequisites. For larger chips with perhaps several hundred pads this is not so easy. The minimum pad interval for bumping is currently 200µm; should this distance be reduced it is possible to undertake a "rewiring" of the chip and to turn it into a micro BGA. On large surface chips the number of chips also plays an essential role. The greater the chip surface area, the more important the relation between bump number/bump height and the pad number in order to achieve perfect quality results during production.
Flip chips can be affixed to different substrates. When selecting a substrate it is important to consider how it behaves in relation to the chip during changes in temperature. If we consider the following and assume a Tk 1 for silicon, then Al 02 ceramic is valued at Tk3, glass-fibre reinforced epoxy resin (PCB) at Tk 10 - 13 and kapton film (flexible board card) at Tk 18 - 23. This clearly shows that the choice of substrate is of great importance when considering the intended use. Stable relationships for service life are therefore primarily only achievable with the additionally embedding of the chip: by underfiller, distribution of the bumps size of the pads and their intervals and thus the corresponding Ni/Au, the correct bump height in relationship to the chip size optimum layout on the base.
|What can be achieved with flip chips today
As the assembly surface of a flip chip takes up only slightly more space than the actual chip size, the packing density in comparison to bond technology can be increased by up to 30% and in favourable circumstances even more. This advantage is only limited by physical influences, such as for example crosstalk and loss of performance. If a greater number of tracker conductors must lead to a chip, it is more sensible, seen from an ASIC application perspective, to deploy several small chips rather than one large one. Not only does this save space for the less required track conductors, but the stability of small chips is far greater as far as assembly is concerned. We now know how bumping can be carried out in a technically fully-developed form. We also know that the use of flip chips marks the beginning of a new technology in the field of microelectronics. This is why we have already employed these chips successfully in measuring and control areas, in sensor modules and many areas besides for ambient temperatures of- 20°C to 85°C. The next stage for us is their application with far greater ambient temperatures.